*, Abhilasha, and Mr. Sudharshan K M. “A Review of an Efficient 8-Bit Vedic Multiplier Using Reversible Logic”. IJRDO - Journal of Electrical And Electronics Engineering 1, no. 5 (May 31, 2015). Accessed December 23, 2024. http://cpcontacts.ijrdo.org/index.php/eee/article/view/397.